Node retainer circuit incorporating RRAM

ABSTRACT

A retainer node circuit is provided that can retain state information of a volatile circuit element (e.g., a flip-flop, latch, switch, register, etc.) of an electronic device for planned or unplanned power-down events. The retainer node circuit can include a resistive-switching memory cell that is nonvolatile, having very fast read and write performance. Coupled with power management circuitry, the retainer node circuit can be activated to receive and store a signal (e.g., bit) output by the volatile circuit element, and activated to output the stored signal. Various embodiments disclose non-volatile retention of state information for planned shut-down events as well as unplanned shut-down events. With read and write speeds in the tens of nanoseconds, sleep mode can be provided for volatile circuit elements between clock cycles of longer time-frame applications, enabling intermittent power-down events between active periods. This enables reduction in power without loss of activity for an electronic device.

PRIORITY CLAIM

The present application for patent is a division of, and claims priorityto, U.S. patent application Ser. No. 15/013,123 entitled “A NodeRetainer Circuit Incorporating RRAM” and filed Feb. 2, 2016, whichclaims the benefit of priority to U.S. Provisional Patent ApplicationSer. No. 62/111,632 entitled “A Node Retainer Node Incorporating RRAM”and filed Feb. 3, 2015, the disclosures of which are hereby incorporatedherein by reference in their respective entireties and for all purposes.

TECHNICAL FIELD

The subject disclosure relates generally to non-volatile memory, and asone illustrative example, a method and system for retaining state usinga resistive random access memory cell.

BACKGROUND

The inventor(s) of the present disclosure have proposed models oftwo-terminal memory devices that he expects to operate as viablealternatives to various memory cell technologies, such as metal-oxidesemiconductor (MOS) type memory cells employed for electronic storage ofdigital information. Models of memory cells using two-terminal memorysuch as resistive-switching memory devices among others, are believed bythe inventor(s) to provide some potential advantages over purelynon-volatile FLASH MOS type transistors, including smaller die size,higher memory density, faster switching (e.g., from a relativelyconductive state to a relatively non-conductive state, or vice versa),good data reliability, low manufacturing cost, and other advantages, forexample.

One memory model proposed by the assignee of the present disclosure isresistive switching memory. The inventor(s) believes resistive switchingmemory can hold substantial advantages over competing technologies inthe semiconductor electronics industry, including, e.g., high densitynon-volatile storage. A resistive switching device, according to somemodels proposed by the inventor(s), has an insulator layer that isprovided between a pair of electrodes and exhibits electrical pulseinduced hysteretic resistance switching effects. The inventor(s) hassuggested that a filament(s) can be formed between the electrodes by adiffusion or drift of ions caused by a suitable external stimulusapplied to the electrodes, which results in a measurable change in theresistance of the structure. Moreover, this change in resistance canremain after removal of the external stimulus, giving the device anon-volatile characteristic in a programmed state. The inventors arecurrently involved in research and development to explore additionalcharacteristics and advantages of two-terminal memory in general.

SUMMARY

The following presents a simplified summary of the specification inorder to provide a basic understanding of some aspects of thespecification. This summary is not an extensive overview of thespecification. It is intended to neither identify key or criticalelements of the specification nor delineate the scope of any particularembodiments of the specification, or any scope of the claims. Itspurpose is to present some concepts of the specification in a simplifiedform as a prelude to the more detailed description that is presented inthis disclosure.

Various embodiments disclosed herein provide a method for retainingstate information using a retainer node circuit with a resistiveswitching memory cell. The method can comprise applying a write voltageto gates of a first transistor and a second transistor, wherein theresistive memory cell is between the first transistor and the secondtransistor. The method can also comprise receiving an inverted input atthe drain or source of the first transistor and an input at the drain orsource of the second transistor, wherein the inverted input and anassociated input voltage are based on a state of a device connected tothe retainer node circuit. The method can further comprise writing thestate of the device to the resistive switching memory cell based on avoltage polarity difference between the input and the inverted input.

In another embodiment, a method for reading retained state informationusing a retainer node circuit with a resistive switching memory cell isprovided. The method can comprise activating a first transistor, asecond transistor and a third transistor, wherein a source of the secondtransistor and a drain of the third transistor are connected to theresistive switching memory cell and wherein the third transistor is alsoconnected to ground, and wherein a source of the first transistor and adrain of the second transistor are connected to an output node. Themethod can include applying a first read signal to a gate of the firsttransistor. The method can include applying a second read signal torespective gates of the second transistor and the third transistor. Themethod can include applying a read voltage to a drain of the firsttransistor. The method can include measuring a voltage at the outputnode in response to applying the read voltage, the first read signal andthe second read signal. The method can include determining the retainedstate information from the voltage at the output node. The method caninclude outputting to the output node the retained state informationstored in the resistive switching memory cell in response to the voltageat the output node, wherein the output node is at zero voltage inresponse to the resistive switching memory cell being in a conductivestate, and wherein the output node is at the read voltage in response tothe resistive switching memory cell being in a resistive state.

In another embodiment, a non-volatile node retainer circuit can includean input node connected to an output node of a volatile multi-statedevice. The node retainer circuit can also include a write activationcircuit configured, in response to a write voltage, to write an outputsignal at the output node of the volatile multi-state device to anon-volatile, two-terminal memory cell, wherein writing the outputsignal is performed in 50 nanoseconds or less and wherein thenon-volatile, two-terminal memory cell stores the output signal as astored signal. The node retainer circuit can also include a readactivation circuit configured, in response to a read voltage, to outputthe stored signal from the non-volatile, two-terminal memory cell and apower management logic configured to apply the write voltage to thewrite activation circuit in response to determination of a plannedpower-down event or an unplanned power-down event associated with thevolatile multi-state device.

In another embodiment, a method for reading retained state informationusing a retainer node circuit with a resistive switching memory cell caninclude applying a read voltage across the resistive switching memorycell. The method can include driving output of the resistive switchingmemory cell onto an output of the retainer node circuit. The method canalso include blocking input of the retainer node circuit from drivingthe output of the retainer node circuit while the resistive switchingmemory cell is being read.

In another embodiment, a method for writing data from a volatile statedevice to a non-volatile memory element can include activating a writecircuit associated with the volatile state device and the non-volatilememory element. The method can also include receiving an output from thevolatile memory element representing the data and applying the output toa first terminal of a bipolar non-volatile memory element. The methodcan also include applying an inverse of the output to a second terminalof the bipolar non-volatile memory element, wherein applying the outputto the first terminal and the inverse of the output to the secondterminal further comprises at least one of writing a zero to thenon-volatile memory element in response to the data being a low signalor writing a one to the non-volatile memory element in response to thedata being a high signal.

The following description and the drawings set forth certainillustrative aspects of the specification. These aspects are indicative,however, of but a few of the various ways in which the principles of thespecification may be employed. Other advantages and novel features ofthe specification will become apparent from the following detaileddescription of the specification when considered in conjunction with thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Various aspects or features of this disclosure are described withreference to the drawings, wherein like reference numerals are used torefer to like elements throughout. In this specification, numerousspecific details are set forth in order to provide a thoroughunderstanding of this disclosure. It should be understood, however, thatcertain aspects of the subject disclosure may be practiced without thesespecific details, or with other methods, components, materials, etc. Inother instances, well-known structures and devices are shown in blockdiagram form to facilitate describing the subject disclosure;

FIG. 1 illustrates a block diagram of an example retainer node circuitin accordance with various aspects described herein.

FIG. 2 illustrates a schematic diagram of an example retainer nodecircuit with a RRAM memory cell in accordance with various aspectsdescribed herein.

FIG. 3 illustrates a timeline showing timing of operations of a retainernode circuit in accordance with various aspects described herein.

FIG. 4 illustrates a timeline showing timing of operations of a retainernode circuit in accordance with various aspects described herein.

FIG. 5 illustrates a block diagram of an example retainer node circuitin accordance with various aspects described herein.

FIG. 6 illustrates a block diagram of an example retainer node circuitin accordance with various aspects described herein.

FIG. 7 illustrates a block diagram of an example retainer node circuitin accordance with various aspects described herein.

FIG. 8 illustrates a flowchart of an example method for retaining stateinformation using a retainer node circuit according to one or moreembodiments disclosed herein.

FIG. 9 illustrates a flowchart of an example method for reading retainedstate information using a retainer node circuit according to one or moreembodiments disclosed herein.

FIG. 10 illustrates a flowchart of an example method for readingretained state information using a retainer node circuit with aresistive switching memory cell according to one or more embodimentsdisclosed herein.

FIG. 11 illustrates a flowchart of an example method for reading writingdata from a volatile state device to a non-volatile memory elementaccording to one or more embodiments disclosed herein.

FIG. 12 depicts a block diagram of a sample operating environment forfacilitating implementation of one or more aspects disclosed herein.

FIG. 13 illustrates a block diagram of an example computing environmentthat can be implemented in conjunction with various embodiments.

DETAILED DESCRIPTION Overview

This disclosure relates to a retainer node circuit that can retain stateinformation of a volatile multi-state component (e.g., a flip-flop, alatch, a configuration register, and so forth) of an electronic device,following power-down of the electronic device. The retainer node circuitcan include a non-volatile, resistive-switching memory cell (alsoreferred to herein as a resistive memory cell, resistive random accessmemory, or the like). The retainer node circuit can comprise an array ofnon-volatile memory elements for a set of volatile multi-statecomponents of the electronic device. When suitable for power managementconfigurations, state information stored in the volatile multi-statecomponents can quickly be written to the non-volatile memory elementsfor storage, allowing the volatile multi-state components of theelectronic device to be shut down. Utilizing resistive-switching memoryas the non-volatile memory elements, transfer of state information tostorage memory can be implemented very quickly (e.g., 20 ns or less),with very little power consumption. Further, upon system restoration,state information is read back from the non-volatile memory elementsback to the volatile multi-state components also very quickly (e.g., 20to 50 ns) and with low power consumption. The quick write and read-backtimes (e.g., under 70 ns combined) can enable a new paradigm inpower-cycling, since the read-write time to non-volatile memory (e.g.,70 ns) is on a time scale that is several orders of magnitude shorterthan that of application-level operations (e.g., wireless signaling,application processes, etc.).

As one illustrative example, an electronic device can perform wirelesssignaling on the second half of every microsecond without interruption,even where the first half of every microsecond is spent with volatilemulti-state elements in sleep mode (e.g., powered-down). Less than 100ns of the 0.5 us sleep period is consumed by writing to and reading fromthe non-volatile memory, leaving more than 400 ns of each microsecond atreduced power (or no power) operation. This can provide significantpower savings for electronic devices, and particularly useful fordevices that operate for long periods on battery power.

In various embodiments, the retainer node circuit can include anon-volatile memory cell having an input connected in parallel to anoutput node of a volatile multi-state component (e.g., flip-flop, latch,switch, register, etc.). Upon activation of a first set of transistorsof the retainer node circuit (e.g., write transistors), a signal at theoutput node of the volatile multi-state component is written to thenon-volatile memory cell. In an embodiment, the amount of time it takesfor the retainer node circuit to write the state of a flip-flop or latchto a non-volatile, resistive-switching memory cell can be about 20nanoseconds or less.

According to some embodiments, upon restoration of power to the set ofvolatile multi-state components, a second set of transistors (e.g., readtransistors) can output a signal stored at the non-volatile memory cellback to the output node of the volatile multi-state component. In theseembodiments, outputting the signal from the non-volatile memory cellback to the output node of the volatile multi-state component restoresthe output node to the state that existed prior to the above-describedwrite operation. In alternative embodiments, the second set oftransistors can output the signal stored at the non-volatile memory cellback to an input node of the volatile-multi-state component, in effectwriting the stored signal back to the volatile multi-state componentitself. Example circuit configurations for implementing these and otherfeatures are described herein.

In an embodiment, read or write voltages can be applied to the retainernode circuit from outside the circuit, such as from a power managementcontroller that activates the write and read signals upon entering powerdown and power up cycles respectively, of a power management protocol(e.g., planned power-down, planned power-up, etc.). In an embodiment,the power management controller can monitor power source power levels,and implement the write voltage in response to determining a powerfailure event (e.g., unplanned power-down). The power failure event can,for instance, be determined in response to satisfaction of one or morepredefined criterion(ia), such as a measured Vcc voltage source fallingbelow a predetermined threshold, or other suitable criterion. In otherembodiments, the retainer node circuit or other circuit can contain aseparate power source (e.g., battery, capacitor, etc.) and simple writelogic configured to write volatile state information to non-volatilememory in response to determination of the power failure event,independently of the main controller (e.g., to maximize efficiency andspeed in preserving state information for the unplanned power-down).

In various embodiments, a disclosed resistive-switching memory cell canbe a filamentary-based device. One example of a filamentary-based devicecan comprise: a conductive layer, e.g., metal, doped p-type (or n-type)silicon (Si) bearing layer (e.g., p-type or n-type polysilicon, p-typeor n-type polycrystalline SiGe, etc.), a resistive switching layer (RSL)and an active metal layer capable of being ionized. Under suitableconditions, the active metal layer can provide filament forming ions tothe RSL. In such embodiments, a conductive filament (e.g., formed by theions) can facilitate electrical conductivity through at least a subsetof the RSL, and a resistance of the filament-based device can bedetermined by a tunneling resistance between the filament and theconductive layer, or by an inherent resistivity of a conductive shortthrough the RSL (e.g., formed by the ions forming the filament withinthe RSL).

In various embodiments of a non-volatile memory cell of the presentdisclosure, a p-type or n-type Si bearing layer can include a p-type orn-type polysilicon, p-type or n-type polycrystalline SiGe, or the like.A RSL (which can also be referred to in the art as a resistive switchingmedia (RSM)) can comprise, e.g., an undoped amorphous Si layer, asemiconductor layer having intrinsic characteristics, a Si sub-oxide(e.g., SiOx wherein x has a value between 0.1 and 2), and so forth.Other examples of materials suitable for the RSL could includeSi_(X)Ge_(Y)O_(Z) (where X, Y and Z are respective suitable positivenumbers), a silicon oxide (e.g., SiO_(N), where N is a suitable positivenumber), amorphous Si (a-Si), amorphous SiGe (a-SiGe), TaO_(B) (where Bis a suitable positive number), HfO_(C) (where C is a suitable positivenumber), TiO_(D) (where D is a suitable number), Al₂O_(E) (where E is asuitable positive number) and so forth, or a suitable combinationthereof. In various embodiments, the RSL includes a number of materialvoids or defects.

An active metal layer for a filamentary-based memory cell can include,among others: silver (Ag), gold (Au), titanium (Ti), titanium-nitride(TiN) or other suitable compounds of titanium, nickel (Ni), copper (Cu),aluminum (Al), chromium (Cr), tantalum (Ta), iron (Fe), manganese (Mn),tungsten (W), vanadium (V), cobalt (Co), platinum (Pt), hafnium (Hf),and palladium (Pd). Other suitable conductive materials, as well ascompounds, alloys, or combinations of the foregoing or similar materialscan be employed for the active metal layer in some aspects of thesubject disclosure. Some details pertaining to embodiments of thesubject disclosure similar to the foregoing example(s) can be found inthe following U.S. patent applications that are licensed to the assigneeof the present application for patent: application Ser. No. 11/875,541filed Oct. 19, 2007 and application Ser. No. 12/575,921 filed Oct. 8,2009, each of which are incorporated by reference herein in theirrespective entireties and for all purposes.

The inventors of the subject application are familiar with additionalnon-volatile, two-terminal memory structures. Ferroelectric randomaccess memory (RAM) is one example. Some others includemagneto-resistive RAM, organic RAM, phase change RAM and conductivebridging RAM, and so on. Two-terminal memory technologies have differingadvantages and disadvantages, and trade-offs between advantages anddisadvantages are common. For instance, various subsets of these devicescan have relatively fast switching times, good durability, high memorydensity, low cost fabrication, long life, or the like, or combinationsthereof. Meanwhile, the various subsets can also be difficult tofabricate, have compatibility problems with many common CMOS fabricationprocesses, poor read performance, small on/off resistance ratios (e.g.,leading to small sensing margin) or poor thermal stability, as well asother challenges. Though resistive-switching memory technology isconsidered by the inventors to be one of the best technologies havingthe most benefits and least detriments, other non-volatile two-terminalmemory technologies, can be utilized for some of the disclosedembodiments, where suitable to one of ordinary skill in the art.

Non-Limiting Examples of Retainer Node Circuit Containing a ResistiveSwitching Memory Cell That Stores State Information

Various aspects or features of this disclosure are described withreference to the drawings, wherein like reference numerals are used torefer to like elements throughout. In this specification, numerousspecific details are set forth in order to provide a thoroughunderstanding of this disclosure. It should be understood, however, thatcertain aspects of disclosure may be practiced without these specificdetails, or with other methods, components, materials, etc. In otherinstances, well-known structures and devices are shown in block diagramform to facilitate describing the subject disclosure.

Referring now to the drawings, in FIG. 1 illustrated is a block diagram100 of an example retainer node circuit 106 in accordance with variousaspects described herein. Retainer node circuit 106 can include aresistive-switching memory cell (e.g., resistive random access memory,and so on) that is a non-volatile memory cell that saves stateinformation associated with a flip-flop or latch in a computing device.In an embodiment, the retainer node circuit 106 can save the stateinformation at an input 102 and write it to an resistive-switchingmemory cell in the retainer node circuit during a power down cycle, andthen a flip-flop/latch at that output 104 can determine the saved stateinformation from the retainer node circuit 106 during a bootup or powerup cycle.

In an embodiment, an input node of the retainer node circuit 106 can beconnected to an output node of a volatile multi-state device (e.g., atinput 102). A write activation circuit in the retainer node circuit 106can be configured, in response to a write voltage, to write an outputsignal at the output node of the volatile multi-state device connectedto input 102 to a non-volatile, two-terminal memory cell in the retainernode circuit 106. The writing of the output signal is performed in 50nanoseconds or less (e.g., about 25 ns, about 20 ns, etc.) and thenon-volatile, two-terminal memory cell stores the output signal as astored signal. A read activation circuit in the retainer node circuit106 can then be configured, in response to a read voltage, to output thestored signal from the non-volatile, two-terminal memory cell to theoutput 104 which can be connected to the input of another volatilemulti-state device connected to the output 104. The retainer nodecircuit can include a power management logic or circuit configured toapply the write voltage to the write activation circuit in response todetermination of a planned power-down event or an unplanned power-downevent associated with the volatile multi-state device.

In an embodiment, the input multi-state device/latch 102 and the outputmulti-state device/latch 104 can be the same latch. Therefore, theretainer node circuit 106 writes the state information of the latch intomemory, and then upon booting or powering up, the retainer node circuit106 restores the state information to the flip-flop/latch that waspowered down.

Turning to FIG. 2, illustrated is a schematic diagram 200 of an exampleretainer node circuit 204 with an RRAM memory cell 214 in accordancewith various aspects described herein.

The retainer node circuit 204 can include a resistive random accessmemory cell that is a non-volatile memory cell that saves stateinformation associated with a flip-flop or latch in a computing device.In an embodiment, the retainer node circuit 204 can save the stateinformation from an input 202 and write it to the RRAM memory cell 214in the retainer node circuit during a power down cycle, and then aflip-flop/latch at that output 226 can determine the saved stateinformation from the retainer node circuit 204 during a bootup or powerup cycle by applying a read voltage signal RD_(RRAM) to the retainernode circuit 204.

During normal operation, at a time other than the power down or power upsign, the node retainer circuit is effectively disconnected from theinput/output 202/226 circuit. When a power down sequence has beeninitiated however, or in response to the node retainer circuitdetermining that a supply voltage has decreased below a predeterminedthreshold, a write voltage WR_(RRAM) can be applied to the gates oftransistors 206 and 208. Applying the WR_(RRAM) voltage in this waycloses the circuit on the right hand side of the retainer node circuit204 and enables retainer node circuit 204 to write a signal at the input202 to the resistive switching memory cell 214. In the embodiment ofFIG. 1, writing the signal from the input 202 is accomplished by thefollowing circuit logic. The signal from the input 202 is inversed atinverter 210, and is connected through the transistor 206 (which isclosed in response to the write voltage) to the top of the resistiveswitching memory cell 214. Accordingly, retainer node circuit 204 isconfigured to apply the inverse of the signal at input 202 to a topterminal of resistive switching memory cell 214. The inverted signalfrom the input 202 is then inverted again at inverter 212 and passesthrough the transistor 208 (which is also closed in response to thewrite voltage) to a bottom terminal of the resistive switching memorycell 214. This signal at the bottom terminal, having passed through theinverter 212, is opposite in polarity to the signal at the top terminalof the resistive switching memory cell 214 and the difference, or bias,programs the resistive switching memory cell 214 to either be in aresistive or conductive state, depending on the initial signal from theinput 202 (and, e.g., the orientation of resistive switching memory cell214).

It should be appreciated that the conductive/resistive state of theresistive switching memory cell 214 can be assigned by convention to alow/high state of input 202, or vice-versa, by convention. Reversingorientation of resistive switching memory cell 214 (e.g., where anactive metal donating filament-forming particles is at the topelectrode, in one embodiment, or at the bottom electrode, in anotherembodiment) can serve to change the association of cell state to bitconvention (e.g., whether high or low), as one example. It should beappreciated that the present disclosure is not limited by the cellstate—bit convention chosen, as other conventions can be utilized andare considered within the scope of the subject disclosure.

The resistive or conductive state of the resistive switching memory cell214 thus reflects the binary state of the flip-flop or latch associatedwith the input 202. This entire procedure of writing to the resistiveswitching memory cell 214 can take about 20 ns or less in some disclosedembodiments, which is far superior to earlier versions of memory-basedstate retainer solutions. After the write procedure is complete, thewrite voltage WR_(RRAM) is removed to once again open transistors 206,208 and deactivate the right side of retainer node circuit 204.

When the system is powering back up, a read voltage RD_(RRAM) can beapplied to the gates of transistors 216 and 218 which effectivelyactivates the left hand side of the retainer node circuit 214 by closingtransistors 216, 218. In addition, the RD_(RRAM) voltage can be appliedto a transmission gate 220 which blocks the signal at input 202 frominterfering with the read (e.g., by isolating the signal at input 202from the common node at the center of schematic diagram 200, just to theright of transmission gate 220). A reversed RD_(RRAM) voltage,RDb_(RRAM) can also be applied to pmos transistor 222, which connects aread voltage source V_(read) to the common node of schematic diagram 200(and consequently the input of retainer node circuit 204). RDb_(RRAM)can be the inverted, or active low version of RD_(RRAM). If theresistive switching memory cell 214 is in a conductive state, sincetransistor 218 is grounded, the V_(read) signal will be pulled down toground through the conducting resistive switching memory cell 214, andthe voltage as measured at the common node and at the output at 226 willbe zero (or approximately zero). By contrast, if the resistive switchingmemory cell 214 is in a resistive state, the voltage as measured at theoutput 226 will be the approximately equal in magnitude to V_(read).Schematic diagram 200 is configured so that the absence or presence of aV_(read) at output 226 reflects the state of the flip-flop or latch(e.g., the signal at input 202) at the time of power down.

Resistive switching memory cell 214 can be a two-terminal deviceconfigured to be operable in response to a suitable electric signalapplied at one or more of two terminals of resistive switching memorycell 214. In various disclosed embodiments, resistive switching memorycell 214 can have a non-linear I-V response, in which resistiveswitching memory cell 214 exhibits current within a first range inresponse to a first range of voltage magnitudes, and current within asecond range (e.g., much higher in magnitude than the first range) inresponse to a second range of voltage magnitudes. The first range ofvoltage magnitudes and second range of voltage magnitudes can bedistinguished, as one example, by a threshold voltage, or a thresholdrange of voltages (e.g., having magnitude(s) between the first range ofvoltage magnitudes and the second range of voltage magnitudes). Inaddition, resistive switching memory cell 214 can be characterized by awrite time of less than about 50 ns, and equal to or below 20 ns in someembodiments. Resistive switching memory cell 214 can alternatively oradditionally be characterized by a read time of less than about 50 ns,and equal to or below 20 ns in one or more embodiments.

In one or more embodiments, the top electrode and bottom electrode ofresistive switching memory cell 214 can comprise a material(s) providingor facilitating provision of mobile atoms or ions in response to asuitable stimulus. Examples of suitable stimuli can include an electricfield (e.g. a programming voltage), joule heating, a magnetic field, orother suitable stimuli for directed or partially directed particlemotion. In at least one embodiment, particle mobility can be in responseto undirected or partially undirected dispersion, or similar phenomena.

Examples of suitable materials for the top electrode or bottom electrodeof resistive switching memory cell 214 can include a noble metal (e.g.,Ag, Pd, Pt, Au, etc.) or a metal alloy containing noble metal in part(e.g., Ag—Al, Ag—Pd—Cu, Ag—W, Ag—Ti, Ag—TiN, Ag—TaN, and so forth). Anoble metal or alloy thereof can be utilized to facilitate mitigatedinteraction between the top electrode or the bottom electrode and aswitching layer of resistive switching memory cell 214 situated betweenthe top electrode and the bottom electrode, for instance. This mitigatedparticle interaction can facilitate improved longevity and reliabilityfor resistive switching memory cell 214, as one example. Another exampleof a suitable material for the top electrode or the bottom electrode caninclude a material with relatively fast diffusing particles. Fasterdiffusion can include, for instance, a capacity to move among defectsites (e.g., voids or gaps in molecular material) within a solid,facilitating dispersion of the relatively fast diffusion particlesabsent a suitable aggregating force, for instance (e.g., an externalvoltage of greater than a threshold magnitude). Materials withrelatively fast diffusing particles can facilitate fast state switchingof resistive switching memory cell 214 (e.g., from a non-conductivestate to a conductive state), at lower bias values. Examples of suitablefast diffusing materials can include Ag, Cu, Au, Co, Ni, Al, Fe, or thelike, suitable alloys thereof, or suitable combinations of theforegoing. In a further embodiment, resistive switching memory cell 214can comprise one or more barrier layers to mitigate oxidation or otherform of material degradation, diffusion mitigation layers to mitigatediffusion of atoms (e.g., metal atoms, such as Cu) out of resistiveswitching memory cell 214, or maintain such atoms within desiredportions of resistive switching memory cell 214, or the like.

In at least one embodiment, the top electrode of resistive switchingmemory cell 214 can be comprised of the same material or substantiallythe same material as the bottom electrode of resistive switching memorycell 214. In other embodiments, the top electrode and bottom electrodecan be different materials. In still other embodiments, the topelectrode and bottom electrode can be at least in part the samematerial, and in part different materials. For instance, the topelectrode could comprise a suitable conductive material, and the bottomelectrode could at least in part comprise an alloy of the suitableconductive material, or the suitable conductive material in combinationwith another suitable conductor, as an illustrative example.

In response to a suitable signal applied at resistive switching memorycell 214, resistive switching memory cell 214 can transition from anon-conducting state having a high electrical resistance and a firstcurrent (or a first range of currents), to a relatively-conducting statehaving a lower electrical resistance and a second current (or a secondrange of currents). In various embodiments, a current ratio of the firstcurrent to the second current (also referred to as an on/off currentratio) can be at least about 1,000 or more. In other embodiments theon/off current ration can be 1:10,000, 1:100,000, or even greaterproportions.

Turning now to FIG. 3, illustrated is a timeline 300 showing timing ofoperations of a retainer node circuit in accordance with various aspectsdescribed herein. The timeline 300 shows activity of various componentsand functions of the retainer node circuit as described above withregard to FIG. 2 along a spectrum time, generally separated into a powerdown time, and a power up time. At 302, the PWR represents the power tothe system, and is generally on except for a length of time between thepower down and power up cycles. Since the resistive switching memorycell 214 is non-volatile, and can save the state of the node for a longperiod of time, the time during a power off can be significant. Althoughin some embodiments, power off time can be relatively short, such as afew hundred nanoseconds. In these latter embodiments, power-on andpower-off can be cycled frequently, for instance every microsecond orevery few microseconds, to achieve significant power savings withminimal impact to device operation. This frequent cycling of power-downoperations can be implemented in conjunction with longer durationpower-off operations, such as when applications of an associatedelectronic device are not operating.

The CLK 304 represents the clock signal and is present near thebeginning of the power down cycle, and near the end of the power upsignal, before and after the state information has been saved andrecovered from the resistive switching memory cell 214 by the retainernode circuit 204.

The RSTb 306 represents the reset cycle in between the power down andpower up cycles. The IN 308 represents the input, and OUT 310 representsthe output. The input 308 is generally not known by the retainer nodecircuit 204 until the WR_(RRAM) signal 312 is applied in the power downcycle. Once the WR_(RRAM) 312 signal is applied to the transistors ofthe retainer node circuit 204, the state of the input 308 is written tothe RRAM 314, which stores the state until rewritten.

During the power up cycle, a RD_(RRAM) signal 316 is applied to thetransistors of the retainer node circuit 204, and the state stored inthe RRAM 314 is applied to the output 310, and once the clock 304 startsagain, the state of the input and output 308 and 310 sequentially changein time with the clock signal 304.

Turning now to FIG. 4, illustrated is a timeline 400 showing timing ofoperations of a retainer node circuit in accordance with various aspectsdescribed herein. The timeline 400 shows a timing diagram topreconfigure the state of the flip-flop or latch into the RRAM 414.

At 402, the PWR represents the power to the system, and is generally onexcept for a length of time between the programming cycle and power upcycles. Since the resistive switching memory cell 414 is non-volatile,and can save the state of the node for a long period of time, the timeduring a power off can be significant.

The CLK 406 represents the clock signal and is present near the end ofthe power up cycle, after the state information has been recovered fromthe resistive switching memory cell 414 by the retainer node circuit.The CLK 406 is also active very briefly in the programming cycle to setthe state at the input 408.

The RSTb 404 represents the reset cycle in between the programming cycleand power up cycles. The IN 408 represents the input, and OUT 410represents the output. The input 408 is generally not known until theWR_(RRAM) signal 412 is applied in the programming cycle. Once theWR_(RRAM) 412 signal is applied, the state of the input 348 is writtento the RRAM 414, which stores the state until rewritten.

During the power up cycle, a RD_(RRAM) signal 416 is applied, and thestate stored in the RRAM 414 is applied to the output 410, and once theclock 406 starts again, the state of the input and output 408 and 410sequentially change in time with the clock signal 406.

Turning now to FIG. 5, illustrated is a block diagram 500 of an exampleretainer node circuit in accordance with various aspects describedherein. State retainer 504, which can correspond to the retainer nodecircuit 204 in some embodiments, is provided to retain the stateinformation of a data flip flop 502 which stores state informationreceived at D and provides the state information at Q. The stateretainer 504 saves the state information received at Q when a WR_(RRAM)signal is applied until a power up cycle initiates. When the power upcycle initiates, the RD_(RRAM) signal is applied and the state retainer504 provides the output, and combinational logic 506 deciphers theoutput to determine the state information of data flip flop 502, andthen the data flip flop 508 receives the state information from thecombinational logic 506, and the power up cycle has completed.

Turning now to FIG. 6, illustrated is a block diagram 600 of an exampleretainer node circuit in accordance with various aspects describedherein. Diagram 600 is similar to the embodiment shown in FIG. 5, butthat there is only one data flip flop 604. State retainer 602 stores thestate information of data flip flop 604 and then upon powering up orbooting up, the state retainer information provides the stateinformation to data flip flop 604.

Turning now to FIG. 7, illustrated is a block diagram 700 of an exampleretainer node circuit 706 in accordance with various aspects describedherein. Retainer node circuit 706 stores the state information of masterlatch 702 and then upon powering up or booting up, the state informationstored in the retainer node circuit 706 is provided to slave latch 704.

The aforementioned diagrams have been described with respect tointeraction between several components of a memory cell, or memoryarchitectures comprised of such memory cells. It should be appreciatedthat in some suitable alternative aspects of the subject disclosure,such diagrams can include those components and architectures specifiedtherein, some of the specified components/architectures, or additionalcomponents/architectures. Sub-components can also be implemented aselectrically connected to other sub-components rather than includedwithin a parent architecture. Additionally, it is noted that one or moredisclosed processes can be combined into a single process providingaggregate functionality. For instance, a read process or a write processcan comprise an inhibit process, or the like, or vice versa, tofacilitate selective reading or writing to subsets of memory cells on acommon line. Components of the disclosed architectures can also interactwith one or more other components not specifically described herein butknown by those of skill in the art.

In view of the exemplary diagrams described supra, process methods thatcan be implemented in accordance with the disclosed subject matter willbe better appreciated with reference to the flow chart of FIG. 8-11.While for purposes of simplicity of explanation, the methods of FIG.8-11 are shown and described as a series of blocks, it is to beunderstood and appreciated that the claimed subject matter is notlimited by the order of the blocks, as some blocks may occur indifferent orders or concurrently with other blocks from what is depictedand described herein. Moreover, not all illustrated blocks may berequired to implement the methods described herein. Additionally, itshould be further appreciated that the methods disclosed throughout thisspecification are capable of being stored on an article of manufactureto facilitate transporting and transferring such methodologies to anelectronic device. The term article of manufacture, as used, is intendedto encompass a computer program accessible from any suitablecomputer-readable device, device in conjunction with a carrier, storagemedium, or the like, or a suitable combination thereof.

Turning now to FIG. 8, a flowchart of an example method for retainingstate information using a retainer node circuit according to one or moreembodiments disclosed herein is illustrated. Flowchart 800 can begin at802 where the method includes applying a write voltage to respectivegates of a first transistor and a second transistor, wherein theresistive memory cell is between the first transistor and the secondtransistor. At 804, the method includes receiving an inverted input atthe drain or source of the first transistor and an input at the drain orsource of the second transistor, wherein the inverted input and anassociated input voltage are based on a state of a device connected tothe retainer node circuit. At 806 the method includes in response to avoltage polarity difference between the input and the inverted input,writing the state of the device to the resistive switching memory cell.

Turning now to FIG. 9, a flowchart of an example method for readingretained state information using a retainer node circuit according toone or more embodiments disclosed herein. Flowchart 900 can begin at 902where the method includes activating a first transistor, a secondtransistor and a third transistor, wherein a source of the secondtransistor and a drain of the third transistor are connected to theresistive switching memory cell and wherein the third transistor is alsoconnected to ground, and wherein a source of the first transistor and adrain of the second transistor are connected to an output node. At 904the method can include applying a first read signal to a gate of thefirst transistor. At 906, the method can include applying a second readsignal to respective gates of the second transistor and the thirdtransistor. And at 908, the method can include applying a read voltageto a drain of the first transistor. At 910, the method can includemeasuring a voltage at the output node in response to applying the readvoltage, the first read signal and the second read signal. At 912, themethod can include determining the retained state information from thevoltage at the output node. At 914, the method can include outputting tothe output node the retained state information stored in the resistiveswitching memory cell in response to the voltage at the output node,wherein the output node is at zero voltage in response to the resistiveswitching memory cell being in a conductive state, and wherein theoutput node is at the read voltage in response to the resistiveswitching memory cell being in a resistive state.

Turning now to FIG. 10, a flowchart of an example method for readingretained state information using a retainer node circuit with aresistive switching memory cell according to one or more embodimentsdisclosed herein is illustrated. Flowchart 1000 can begin at 1002 wherethe method includes applying a read voltage across the resistiveswitching memory cell. At 1004, the method includes driving output ofthe resistive switching memory cell onto an output of the retainer nodecircuit. At 1006 the method includes blocking input of the retainer nodecircuit from driving the output of the retainer node circuit while theresistive switching memory cell is being read.

Turning now to FIG. 11, flowchart of an example method for readingwriting data from a volatile state device to a non-volatile memoryelement according to one or more embodiments disclosed herein. Flowchart1100 can begin at 1102 where the method includes activating a writecircuit associated with the volatile state device and the non-volatilememory element. At 1104, the method includes receiving an output fromthe volatile memory element representing the data. At 1106 the methodincludes applying the output to a first terminal of a bipolarnon-volatile memory element. At 1108, the method includes applying aninverse of the output to a second terminal of the bipolar non-volatilememory element. At 1110, the method includes wherein applying the outputto the first terminal and the inverse of the output to the secondterminal further comprises at least one of writing a zero to thenon-volatile memory element in response to the data being a low signalor writing a one to the non-volatile memory element in response to thedata being a high signal.

Example Operating Environments

In various embodiments of the subject disclosure, disclosed memoryarchitectures can be employed as a standalone or integrated embeddedmemory device with a CPU or microcomputer. Some embodiments can beimplemented, for instance, as part of a computer memory (e.g., randomaccess memory, cache memory, read-only memory, storage memory, or thelike). Other embodiments can be implemented, for instance, as a portablememory device. Examples of suitable portable memory devices can includeremovable memory, such as a secure digital (SD) card, a universal serialbus (USB) memory stick, a compact flash (CF) card, or the like, orsuitable combinations of the foregoing. (See, e.g., FIGS. 12 and 13,infra).

NAND FLASH is employed for compact FLASH devices, USB devices, SD cards,solid state drives (SSDs), and storage class memory, as well as otherform-factors. Although NAND has proven a successful technology infueling the drive to scale down to smaller devices and higher chipdensities over the past decade, as technology scaled down past 25nanometer (nm) memory cell technology, the inventors have identifiedseveral structural, performance, and reliability problems that becameevident to them. These or similar considerations can be addressed bysome or all of the disclosed aspects.

In order to provide a context for the various aspects of the disclosedsubject matter, FIG. 12, as well as the following discussion, isintended to provide a brief, general description of a suitableenvironment in which various aspects of the disclosed subject matter canbe implemented or processed. While the subject matter has been describedabove in the general context of electronic memory and process methodsfor fabricating or operating the electronic memory, those skilled in theart will recognize that the subject disclosure also can be implementedin combination with other components/layers of memory, memoryarchitectures or process methodologies. Moreover, those skilled in theart will appreciate that the disclosed processes can be implementedwithin a processing system or a computer processor, either alone or inconjunction with a host computer, which can include single-processor ormultiprocessor computer systems, mini-computing devices, mainframecomputers, as well as personal computers, hand-held computing devices(e.g., PDA, smart phone, watch), microprocessor-based or programmableconsumer or industrial electronics, and the like. The illustratedaspects may also be practiced in distributed computing environmentswhere tasks are performed by remote processing devices that are linkedthrough a communications network. However, some, if not all aspects ofthe claimed innovation can be practiced on stand-alone electronicdevices, such as a memory card, FLASH memory module, removable memory,or the like. In a distributed computing environment, program modules canbe located in both local and remote memory storage modules or devices.

FIG. 12 illustrates a block diagram of an example operating and controlenvironment 1200 for a memory cell array 1202 according to aspects ofthe subject disclosure. In at least one aspect of the subjectdisclosure, memory cell array 1202 can comprise a variety of memory celltechnology. Particularly, memory cell array 1202 can comprisetwo-terminal memory such as resistive memory cells with a resistiveswitching medium formed via ion implantation to a conductive polysiliconmaterial, as described herein.

A column controller 1206 can be formed adjacent to memory cell array1202. Moreover, column controller 1206 can be electrically coupled withbit lines of memory cell array 1202. Column controller 1206 can controlrespective bitlines, applying suitable program, erase or read voltagesto selected bitlines.

In addition, operating and control environment 1200 can comprise a rowcontroller 1204. Row controller 1204 can be formed adjacent to columncontroller 1206, and electrically connected with word lines of memorycell array 1202. Row controller 1204 can select particular rows ofmemory cells with a suitable selection voltage. Moreover, row controller1204 can facilitate program, erase or read operations by applyingsuitable voltages at selected word lines.

A clock source(s) 1208 can provide respective clock pulses to facilitatetiming for read, write, and program operations of row control 1204 andcolumn control 1206. Clock source(s) 1208 can further facilitateselection of word lines or bit lines in response to external or internalcommands received by operating and control environment 1200. Aninput/output buffer 1212 can be connected to an external host apparatus,such as a computer or other processing device (not depicted) by way ofan I/O buffer or other I/O communication interface. Input/output buffer1212 can be configured to receive write data, receive an eraseinstruction, output readout data, and receive address data and commanddata, as well as address data for respective instructions. Address datacan be transferred to row controller 1204 and column controller 1206 byan address register 1210. In addition, input data is transmitted tomemory cell array 1202 via signal input lines, and output data isreceived from memory cell array 1202 via signal output lines. Input datacan be received from the host apparatus, and output data can bedelivered to the host apparatus via the I/O buffer.

Commands received from the host apparatus can be provided to a commandinterface 1214. Command interface 1214 can be configured to receiveexternal control signals from the host apparatus, and determine whetherdata input to the input/output buffer 1212 is write data, a command, oran address. Input commands can be transferred to a state machine 1216.

State machine 1216 can be configured to manage programming andreprogramming of memory cell array 1202. State machine 1216 receivescommands from the host apparatus via input/output interface 1212 andcommand interface 1214, and manages read, write, erase, data input, dataoutput, and like functionality associated with memory cell array 1202.In some aspects, state machine 1216 can send and receive acknowledgmentsand negative acknowledgments regarding successful receipt or executionof various commands.

To implement read, write, erase, input, output, etc., functionality,state machine 1216 can control clock source(s) 1208. Control of clocksource(s) 1208 can cause output pulses configured to facilitate rowcontroller 1204 and column controller 1206 implementing the particularfunctionality. Output pulses can be transferred to selected bit lines bycolumn controller 1206, for instance, or word lines by row controller1204, for instance.

The illustrated aspects of the disclosure may also be practiced indistributed computing environments where certain tasks are performed byremote processing devices that are linked through a communicationsnetwork. In a distributed computing environment, program modules orstored information, instructions, or the like can be located in local orremote memory storage devices.

Moreover, it is to be appreciated that various components describedherein can include electrical circuit(s) that can include components andcircuitry elements of suitable value in order to implement theembodiments of the subject innovation(s). Furthermore, it can beappreciated that many of the various components can be implemented onone or more IC chips. For example, in one embodiment, a set ofcomponents can be implemented in a single IC chip. In other embodiments,one or more respective components are fabricated or implemented onseparate IC chips.

In connection with FIG. 13, the systems and processes described belowcan be embodied within hardware, such as a single integrated circuit(IC) chip, multiple ICs, an application specific integrated circuit(ASIC), or the like. Further, the order in which some or all of theprocess blocks appear in each process should not be deemed limiting.Rather, it should be understood that some of the process blocks can beexecuted in a variety of orders, not all of which may be explicitlyillustrated herein.

With reference to FIG. 13, a suitable environment 1300 for implementingvarious aspects of the claimed subject matter includes a computer 1302.The computer 1302 includes a processing unit 1304, a system memory 1306,a codec 1335, and a system bus 1308. The system bus 1308 couples systemcomponents including, but not limited to, the system memory 1306 to theprocessing unit 1304. The processing unit 1304 can be any of variousavailable processors. Dual microprocessors and other multiprocessorarchitectures also can be employed as the processing unit 1304.

The system bus 1308 can be any of several types of bus structure(s)including the memory bus or memory controller, a peripheral bus orexternal bus, or a local bus using any variety of available busarchitectures including, but not limited to, Industrial StandardArchitecture (ISA), Micro-Channel Architecture (MSA), Extended ISA(EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB),Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus(USB), Advanced Graphics Port (AGP), Personal Computer Memory CardInternational Association bus (PCMCIA), Firewire (IEEE 1394), and SmallComputer Systems Interface (SCSI).

The system memory 1306 includes volatile memory 1310 and non-volatilememory 1312, which can employ one or more of the disclosed memoryarchitectures, in various embodiments. The basic input/output system(BIOS), containing the basic routines to transfer information betweenelements within the computer 1302, such as during start-up, is stored innon-volatile memory 1312. In addition, according to present innovations,codec 1335 may include at least one of an encoder or decoder, whereinthe at least one of an encoder or decoder may consist of hardware,software, or a combination of hardware and software. Although, codec1335 is depicted as a separate component, codec 1335 may be containedwithin non-volatile memory 1312. By way of illustration, and notlimitation, non-volatile memory 1312 can include read only memory (ROM),programmable ROM (PROM), electrically programmable ROM (EPROM),electrically erasable programmable ROM (EEPROM), or Flash memory.Non-volatile memory 1312 can employ one or more of the disclosed memorydevices, in at least some embodiments. Moreover, non-volatile memory1312 can be computer memory (e.g., physically integrated with computer1302 or a mainboard thereof), or removable memory. Examples of suitableremovable memory with which disclosed embodiments can be implemented caninclude a secure digital (SD) card, a compact Flash (CF) card, auniversal serial bus (USB) memory stick, or the like. Volatile memory1310 includes random access memory (RAM), which acts as external cachememory, and can also employ one or more disclosed memory devices invarious embodiments. By way of illustration and not limitation, RAM isavailable in many forms such as static RAM (SRAM), dynamic RAM (DRAM),synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), andenhanced SDRAM (ESDRAM) and so forth.

Computer 1302 may also include removable/non-removable,volatile/non-volatile computer storage medium. FIG. 13 illustrates, forexample, disk storage 1314. Disk storage 1314 includes, but is notlimited to, devices like a magnetic disk drive, solid state disk (SSD)floppy disk drive, tape drive, Jaz drive, Zip drive, LS-100 drive, flashmemory card, or memory stick. In addition, disk storage 1314 can includestorage medium separately or in combination with other storage mediumincluding, but not limited to, an optical disk drive such as a compactdisk ROM device (CD-ROM), CD recordable drive (CD-R Drive), CDrewritable drive (CD-RW Drive) or a digital versatile disk ROM drive(DVD-ROM). To facilitate connection of the disk storage devices 1314 tothe system bus 1308, a removable or non-removable interface is typicallyused, such as interface 1316. It is appreciated that storage devices1314 can store information related to a user. Such information might bestored at or provided to a server or to an application running on a userdevice. In one embodiment, the user can be notified (e.g., by way ofoutput device(s) 1336) of the types of information that are stored todisk storage 1314 or transmitted to the server or application. The usercan be provided the opportunity to opt-in or opt-out of having suchinformation collected or shared with the server or application (e.g., byway of input from input device(s) 1328).

It is to be appreciated that FIG. 13 describes software that acts as anintermediary between users and the basic computer resources described inthe suitable operating environment 1300. Such software includes anoperating system 1318. Operating system 1318, which can be stored ondisk storage 1314, acts to control and allocate resources of thecomputer system 1302. Applications 1320 take advantage of the managementof resources by operating system 1318 through program modules 1324, andprogram data 1326, such as the boot/shutdown transaction table and thelike, stored either in system memory 1306 or on disk storage 1314. It isto be appreciated that the claimed subject matter can be implementedwith various operating systems or combinations of operating systems.

A user enters commands or information into the computer 1302 throughinput device(s) 1328. Input devices 1328 include, but are not limitedto, a pointing device such as a mouse, trackball, stylus, touch pad,keyboard, microphone, joystick, game pad, satellite dish, scanner, TVtuner card, digital camera, digital video camera, web camera, and thelike. These and other input devices connect to the processing unit 1304through the system bus 1308 via interface port(s) 1330. Interfaceport(s) 1330 include, for example, a serial port, a parallel port, agame port, and a universal serial bus (USB). Output device(s) 1336 usesome of the same type of ports as input device(s) 1328. Thus, forexample, a USB port may be used to provide input to computer 1302 and tooutput information from computer 1302 to an output device 1336. Outputadapter 1334 is provided to illustrate that there are some outputdevices 1336 like monitors, speakers, and printers, among other outputdevices 1336, which require special adapters. The output adapters 1334include, by way of illustration and not limitation, video and soundcards that provide a means of connection between the output device 1336and the system bus 1308. It should be noted that other devices orsystems of devices provide both input and output capabilities such asremote computer(s) 1338.

Computer 1302 can operate in a networked environment using logicalconnections to one or more remote computers, such as remote computer(s)1338. The remote computer(s) 1338 can be a personal computer, a server,a router, a network PC, a workstation, a microprocessor based appliance,a peer device, a smart phone, a tablet, or other network node, andtypically includes many of the elements described relative to computer1302. For purposes of brevity, only a memory storage device 1340 isillustrated with remote computer(s) 1338. Remote computer(s) 1338 islogically connected to computer 1302 through a network interface 1342and then connected via communication connection(s) 1344. Networkinterface 1342 encompasses wire or wireless communication networks suchas local-area networks (LAN) and wide-area networks (WAN) and cellularnetworks. LAN technologies include Fiber Distributed Data Interface(FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ringand the like. WAN technologies include, but are not limited to,point-to-point links, circuit switching networks like IntegratedServices Digital Networks (ISDN) and variations thereon, packetswitching networks, and Digital Subscriber Lines (DSL).

Communication connection(s) 1344 refers to the hardware/softwareemployed to connect the network interface 1342 to the bus 1308. Whilecommunication connection 1344 is shown for illustrative clarity insidecomputer 1302, it can also be external to computer 1302. Thehardware/software necessary for connection to the network interface 1342includes, for exemplary purposes only, internal and externaltechnologies such as, modems including regular telephone grade modems,cable modems and DSL modems, ISDN adapters, and wired and wirelessEthernet cards, hubs, and routers.

As utilized herein, terms “component,” “system,” “architecture” and thelike are intended to refer to a computer or electronic-related entity,either hardware, a combination of hardware and software, software (e.g.,in execution), or firmware. For example, a component can be one or moretransistors, a memory cell, an arrangement of transistors or memorycells, a gate array, a programmable gate array, an application specificintegrated circuit, a controller, a processor, a process running on theprocessor, an object, executable, program or application accessing orinterfacing with semiconductor memory, a computer, or the like, or asuitable combination thereof. The component can include erasableprogramming (e.g., process instructions at least in part stored inerasable memory) or hard programming (e.g., process instructions burnedinto non-erasable memory at manufacture).

By way of illustration, both a process executed from memory and theprocessor can be a component. As another example, an architecture caninclude an arrangement of electronic hardware (e.g., parallel or serialtransistors), processing instructions and a processor, which implementthe processing instructions in a manner suitable to the arrangement ofelectronic hardware. In addition, an architecture can include a singlecomponent (e.g., a transistor, a gate array, . . . ) or an arrangementof components (e.g., a series or parallel arrangement of transistors, agate array connected with program circuitry, power leads, electricalground, input signal lines and output signal lines, and so on). A systemcan include one or more components as well as one or more architectures.One example system can include a switching block architecture comprisingcrossed input/output lines and pass gate transistors, as well as powersource(s), signal generator(s), communication bus(ses), controllers, I/Ointerface, address registers, and so on. It is to be appreciated thatsome overlap in definitions is anticipated, and an architecture or asystem can be a stand-alone component, or a component of anotherarchitecture, system, etc.

In addition to the foregoing, the disclosed subject matter can beimplemented as a method, apparatus, or article of manufacture usingtypical manufacturing, programming or engineering techniques to producehardware, firmware, software, or any suitable combination thereof tocontrol an electronic device to implement the disclosed subject matter.The terms “apparatus” and “article of manufacture” where used herein areintended to encompass an electronic device, a semiconductor device, acomputer, or a computer program accessible from any computer-readabledevice, carrier, or media. Computer-readable media can include hardwaremedia, or software media. In addition, the media can includenon-transitory media, or transport media. In one example, non-transitorymedia can include computer readable hardware media. Specific examples ofcomputer readable hardware media can include but are not limited tomagnetic storage devices (e.g., hard disk, floppy disk, magnetic strips. . . ), optical disks (e.g., compact disk (CD), digital versatile disk(DVD) . . . ), smart cards, and flash memory devices (e.g., card, stick,key drive . . . ). Computer-readable transport media can include carrierwaves, or the like. Of course, those skilled in the art will recognizemany modifications can be made to this configuration without departingfrom the scope or spirit of the disclosed subject matter.

What has been described above includes examples of the subjectinnovation. It is, of course, not possible to describe every conceivablecombination of components or methodologies for purposes of describingthe subject innovation, but one of ordinary skill in the art canrecognize that many further combinations and permutations of the subjectinnovation are possible. Accordingly, the disclosed subject matter isintended to embrace all such alterations, modifications and variationsthat fall within the spirit and scope of the disclosure. Furthermore, tothe extent that a term “includes”, “including”, “has” or “having” andvariants thereof is used in either the detailed description or theclaims, such term is intended to be inclusive in a manner similar to theterm “comprising” as “comprising” is interpreted when employed as atransitional word in a claim.

Moreover, the word “exemplary” is used herein to mean serving as anexample, instance, or illustration. Any aspect or design describedherein as “exemplary” is not necessarily to be construed as preferred oradvantageous over other aspects or designs. Rather, use of the wordexemplary is intended to present concepts in a concrete fashion. As usedin this application, the term “or” is intended to mean an inclusive “or”rather than an exclusive “or”. That is, unless specified otherwise, orclear from context, “X employs A or B” is intended to mean any of thenatural inclusive permutations. That is, if X employs A; X employs B; orX employs both A and B, then “X employs A or B” is satisfied under anyof the foregoing instances. In addition, the articles “a” and “an” asused in this application and the appended claims should generally beconstrued to mean “one or more” unless specified otherwise or clear fromcontext to be directed to a singular form.

Additionally, some portions of the detailed description have beenpresented in terms of algorithms or process operations on data bitswithin electronic memory. These process descriptions or representationsare mechanisms employed by those cognizant in the art to effectivelyconvey the substance of their work to others equally skilled. A processis here, generally, conceived to be a self-consistent sequence of actsleading to a desired result. The acts are those requiring physicalmanipulations of physical quantities. Typically, though not necessarily,these quantities take the form of electrical or magnetic signals capableof being stored, transferred, combined, compared, and/or otherwisemanipulated.

It has proven convenient, principally for reasons of common usage, torefer to these signals as bits, values, elements, symbols, characters,terms, numbers, or the like. It should be borne in mind, however, thatall of these and similar terms are to be associated with the appropriatephysical quantities and are merely convenient labels applied to thesequantities. Unless specifically stated otherwise or apparent from theforegoing discussion, it is appreciated that throughout the disclosedsubject matter, discussions utilizing terms such as processing,computing, replicating, mimicking, determining, or transmitting, and thelike, refer to the action and processes of processing systems, and/orsimilar consumer or industrial electronic devices or machines, thatmanipulate or transform data or signals represented as physical(electrical or electronic) quantities within the circuits, registers ormemories of the electronic device(s), into other data or signalssimilarly represented as physical quantities within the machine orcomputer system memories or registers or other such information storage,transmission and/or display devices.

In regard to the various functions performed by the above describedcomponents, architectures, circuits, processes and the like, the terms(including a reference to a “means”) used to describe such componentsare intended to correspond, unless otherwise indicated, to any componentwhich performs the specified function of the described component (e.g.,a functional equivalent), even though not structurally equivalent to thedisclosed structure, which performs the function in the hereinillustrated exemplary aspects of the embodiments. In addition, while aparticular feature may have been disclosed with respect to only one ofseveral implementations, such feature may be combined with one or moreother features of the other implementations as may be desired andadvantageous for any given or particular application. It will also berecognized that the embodiments include a system as well as acomputer-readable medium having computer-executable instructions forperforming the acts and/or events of the various processes.

What is claimed is:
 1. A method for reading retained state informationfrom a retainer node circuit that comprises a resistive switching memorycell, the method comprising: activating a first transistor, a secondtransistor and a third transistor, wherein a source of the secondtransistor and a drain of the third transistor are connected to theresistive switching memory cell and wherein the third transistor is alsoconnected to ground, and wherein a source of the first transistor and adrain of the second transistor are connected to an output node; applyinga first read signal to a gate of the first transistor; applying a secondread signal to respective gates of the second transistor and the thirdtransistor; applying a read voltage to a drain of the first transistor;measuring a voltage at the output node in response to applying the readvoltage, the first read signal and the second read signal; determiningthe retained state information from the voltage at the output node; andoutputting to the output node the retained state information stored inthe resistive switching memory cell in response to the voltage at theoutput node, wherein the output node is at zero voltage in response tothe resistive switching memory cell being in a conductive state, andwherein the output node is at the read voltage in response to theresistive switching memory cell being in a resistive state.
 2. Themethod of claim 1, wherein a resistivity of the resistive switchingmemory cell is based on the retained state information programmed duringa write sequence.
 3. The method of claim 1, further comprising:outputting the retained state information to a latch, wherein a firststate corresponds to the read voltage, and a second state corresponds tozero voltage.
 4. The method of claim 1, further comprising: applying theread voltage signal to a transmission gate which blocks an input from alatch.
 5. The method of claim 1, further comprising: applying the firstread signal, the read voltage and the second read signal in response todetermining that a boot-up sequence has initiated.
 6. The method ofclaim 1, further comprising providing the retained state informationfrom the output node to a volatile memory element having an outputconnected to the retainer node circuit.
 7. The method of claim 6,further comprising writing the retained state information from thevolatile memory element to the resistive switching memory cell prior tothe activating the first transistor, the second transistor and the thirdtransistor, and in response to a condition selected from a groupconsisting essentially of: detecting a non-ordered power loss affectingthe volatile memory element, and receiving a command to save theretained state information from the volatile memory element at theretainer node circuit.
 8. The method of claim 7, wherein providing theretained state information to the volatile memory element comprisesrefreshing the volatile memory element with a bit value maintained atthe volatile memory element prior to the writing the retained stateinformation to the resistive switching memory cell.
 9. The method ofclaim 1, further comprising: applying a write voltage to respectivegates of a fourth transistor and a fifth transistor, wherein theresistive switching memory cell is connected at a first terminal thereofto the fourth transistor and is connected at a second terminal thereofto the fifth transistor; receiving an inverted input at a drain orsource of the fourth transistor and an input at a drain or source of thefifth transistor, wherein the inverted input and an associated inputvoltage are based on a state of a device connected to the retainer nodecircuit; and in response to a voltage polarity difference between theinput and the inverted input, writing the state of the device to theresistive switching memory cell, wherein the retained state informationdetermined in response to the measuring the voltage at the output node,the activating the first, second and third transistors and applying thefirst read signal, second read signal and read voltage, is equivalent tothe state of the device written to the resistive switching memory cell.10. The method of claim 9, further comprising applying the write voltagein response to determining that a supply voltage has fallen below apredetermined threshold.
 11. The method of claim 10, further comprisingdetermining that the supply voltage has increased above thepredetermined threshold.
 12. The method of claim 11, wherein theactivating the first, second and third transistors, applying the firstread signal, the second read signal and read voltage, the measuring thevoltage at the output node, the determining the retained stateinformation and the outputting to the output node the retained stateinformation that is equivalent to the state of the device written to theresistive switching memory cell, is in response to the determining thatthe supply voltage has increased above the predetermined threshold. 13.The method of claim 1, further comprising blocking an input of theretainer node circuit from driving the output node concurrent with theapplying the read voltage.
 14. The method of claim 9, further comprisingupdating the device with a data bit matching the output of the retainernode circuit in conjunction with outputting to the output node theretained state information.
 15. The method of claim 9, furthercomprising applying the write voltage in response to receiving the writevoltage from a controller.
 16. The method of claim 9, furthercomprising: inverting the input with a first inverter between the deviceand the fourth transistor and the fifth transistor; and inverting theinverted input with a second inverter between the fourth transistor andthe fifth transistor.
 17. The method of claim 9, wherein the device isselected from a group consisting essentially of: a switch, a flip-flopand a volatile memory device.
 18. The method of claim 1, furthercomprising: activating a write circuit associated with the device andthe resistive switching memory cell; receiving an output from the devicerepresenting data indicative of a state of the device; applying theoutput to a first terminal of the resistive switching memory cell; andapplying an inverse of the output to a second terminal of the resistiveswitching memory cell, wherein applying the output to the first terminaland the inverse of the output to the second terminal further comprisesat least one of: writing a zero to the resistive switching memory cellin response to the data being a low signal; or writing a one to theresistive switching memory cell in response to the data being a highsignal.
 19. The method of claim 18, further comprising activating thewrite circuit in response to determining that a supply voltage hasfallen below a predetermined threshold.
 20. The method of claim 19,further comprising in response to determining that the supply voltagehas returned to the predetermined threshold: reading the zero or the onefrom the resistive switching memory cell; and refreshing the device withthe zero, or the one, read from the resistive switching memory cell.